An Electrical and Computer Engineering and Mathematics junior at University of California, San Diego seeking to conduct research in the fields of electronics, computers architecture, or mathematics. Interested in driver development, optimization, high performance computing, or computer graphics but open to exploring other areas.
A team managed by Professor Yifeng Cui dedicated to developing and optimizing a world-class earthquake simulation application, and preparing software for future exascale supercomputing facilities
Ported the team's current stencil code to AMD HIP and optimized it for exascale systems
Student assistant in ATG @ NERSC
Analyzed power consumption on NERSC's current Supercomputer Perlmutter to aid in future supercomputing system procurement
Presented findings in a poster to the lab's Computing Sciences Area
Published results to SC23 Sustainable Computing Workshop
Presented additional findings on reduced precision to Computing Sciences Area
Aggregated product data from 12 different internal sources and converted the raw information into experiences for our consumers
Refined the continuous delivery build pipeline and autmated analysis to ensure easier global delivery and scalability of our platform
Developed performant AWS Lambdas with high-throughput architecture
Exposed additional metadata of API calls to data consumers for error handling
Consolidated several modules into a single repository for ease of deployment on AWS Waffle
2MuchCache is UCSD's competition team for the Student Cluster Competition 2022. The SCC22 competition involved running several HPC benchmarks and applications on a custom system we request from sponsors. We must be able to run those workloads as high performance as we can, yet only consume a maximum of 3000W.
Helped setup system monitoring and cooling solution for our cluster
Optimized AMD EPYC CPUs and AMD Instinct Accelerators to run efficiently based on the workload by adjusting clock frequencies
Developed scripts to reproduce a high performance Python framework on our cluster and on Microsoft Azure
Placed 1st in HPL score among 10 teams
Placed 3rd overall among 12 teams
Published a paper to IEEE's Transactions on Parallel and Distributed Systems
TritonLLC is UCSD's competition team for the Student Cluster Competition 2023.
Helped setting up MLPerf
Helped setup and tear down the Hot Chips conference at Stanford
Listened to keynotes from several hardware companies
Met John Hennessy
2-person team managed by Professor Curt Schurgers tasked with developing a website to teach students about difficult analog circuit concepts
Redesigned the frontend for ease of use by students and optimized the backend to send only required data instead of the entire record
Started to port the application from server side rendering to an API with client side rendering
Improved the data validation from user file inputs
Worked on a non-invasive way to track animals in the wild for better understanding of their habits
Developed a performant library to run with minimal power consumption on embedded systems
Bachelors of Science
XORiginal Processor ISA (or XORPI for short) is an instruction set architecture that 2 other members and I developed. It was designed for quickly solving complex problems posed to us in our CSE 141L course at UCSD. The ISA was sketched out by us, then developed with SystemVerilog and simulated using a combination of Verilator and ModelSim. Finally, the processor was synthesized with Intel Quartus.
Developed a whitepaper for an ISA capable of performing parity encoding and decoding as well as pattern matching
Developed the processor model with SystemVerilog, including our custom built XOR unit
Simulated and tested the processor with Verilator
Verified our results with the provided SystemVerilog testbenches in ModelSim
Synthesized our model with Intel Quartus
Built an assembler and debugger for our ISA in C++
Equitable Elevator Controller MK. VII is a model written in VHDL designed for CSE 143 at UCSD. The controller features input processing, direction determination, stop prioritization, floor arrival and direction adjustment, continuous operation, and door control.
Developed using VHDL
Simulated with ModelSim
Wrote a whitepaper describing the elevator controller
Wrote a comprehensive testbench in VHDL and verified the model with ModelSim
Presented my work to 30 peers
Built, tested, and debugged a working 8-bit CPU from scratch using only ICs, hookup wire, and breadboards
Two 8-bit general purpose registers
One 8-bit ALU register
Two conditional jump instructions
Adjustable clock speed (1Hz to 70Hz)
Consumes 10W of power
Built a full-stack deep learning classification web application
Trained a CNN on MNIST using Keras and achieving a validation accuracy of 98.84% after 10 epochs
Converted Keras model to tensorflow.js for deployment
Developed frontend with P5.js, Chart.js, and Bootstrap